Over the last four decades, the density of integrated circuits has increased by a relation known as Moore's law. Stated simply, Moore's law says that the number of transistors on an integrated circuit doubles approximately every 18 months. Thus, as long as the semiconductor industry can continue to uphold this simple “law,” integrated circuits double in speed and power approximately every 18 months. In large part, this remarkable increase in the speed and power of integrated circuits has ushered in the dawn of today's information age.
Unlike laws of nature which hold true regardless of mankind's activities (e.g,. the law of gravity), Moore's law only holds true only so long as innovators overcome the technological challenges associated with it. For example, one recent challenge involves changing from a traditional aluminum interconnect to a copper interconnect to reduce the resistance of the interconnect. Unfortunately, copper is very difficult to etch in a semiconductor process flow. Therefore, damascene processes have been proposed to form copper interconnects.
As shown in FIG. 1a, a typical damascene process consists of forming an interlevel dielectric 12 over a semiconductor body 10. The interlevel dielectric 12 is then patterned and etched to remove the dielectric material from the areas 14 where the interconnect lines are desired, as shown in FIG. 1b. In a dual damascene process, via holes are also formed at this time. Referring to FIG. 1c,a barrier layer 16 is then deposited over the structure including over the dielectric 12 and in the areas 14 where the dielectric has been removed. A copper seed layer 18 is then formed over the barrier layer 16. The copper layer 20 is then formed from the seed layer 18 using, for example, an electroplating process, as shown in FIG. 1d. Chemical-mechanical polishing (CMP) is then used to remove the excess copper and planarize the copper 20. The Copper CMP process is typically divided into Copper removal step and barrier removal step where typically different polishing slurry is used. The Copper removal step is typically further divided into two steps: a high down force step (HDF) when higher polishing down force is used to achieve high polishing rate, hence, high throughput, and a low down-force (LDF) step when lower polishing down force is used to reduce dishing, however, with reduced polishing rate. After the Copper removal step, almost all the excess Copper layer has been removed, as shown in FIG. 1e. Typically an over polish step is used after each of the Cu removal steps to ensure all residue Copper is removed, or all Copper is cleared. As indicated by numeral 22, dishing may be present. The barrier layer 16 on top of the surface is then removed by barrier polishing to eliminate undesired shorting among adjacent Copper trenches. One resulting structure may be seen in FIG. 1f. 
As damascene processing is a recent development, aspects of the process need improvement. One of the most significant challenges in CMP is finding a balance between throughput (i.e., the number of wafers processed) and yield (i.e., the quality of the wafers processed). For Copper CMP process, the challenge is to find an effective polishing time to switch from High Down-Force (HDF) step to Low Down-Force (LDF) step. If the switch from HDF to LDF happens too early, significantly longer time of LDF step has to be used in order to clear the Copper. This would significantly lower the process throughput. On the other hand, if the switch from HDF to LDF happens too late, significant Copper dishing has already been created in the HDF step. This will result in high dishing at the end of LDF step. An optimized process is the one with correct transition point from HDF to LDF so both throughput requirement and dishing requirement can be met.
For example, “dishing” (formation of a dish-like, concave feature in a surface caused by pad bending during polishing) can occur in CMP. One method of preventing dishing is to remove semiconductor material at a very slow rate. While such a slow removal rate can provide for low dishing, it also slows throughput, which potentially limits the manufacturer's income. Conversely, if the semiconductor material is removed at a very fast rate, throughput will be improved but dishing can be more pronounced. Because the dishing may result in metal thickness variation depending on the local pattern density and difficulty in patterning at the next level, removing the semiconductor material at a fast rate also potentially limits the manufacturer's income.
Thus, a method of chemical mechanical polishing that can achieve a balance between throughput and performance is needed.